Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.

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Rob Dekker’s involvement in logic synthesis technology spans more than 20 years. He’s developed a thriving business selling register-transfer-level (RTL) parsers and elaborators to companies offering commercial EDA tools and electronics companies implementing or upgrading their design flows. I spoke with him about trends in the electronics area. Read more at electronicdesign.com

Verific Design Automation specializes in Verilog, VHDL and SystemVerilog language processing sub-systems. Its users develop software where Verific-based technology serves as the front end for a wide range of EDA and FPGA design tools. These tools are used during analysis, simulation, verification, synthesis, emulation and test.

This article discusses the use of Verific technology by our team at the Really Useful Software and Hardware Company. We hope these experiences will be of use to the many other Verific users out there and we also describe our own efforts to extend the technology with a series of ‘apps’ addressing common tool developer issues.

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Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers as the front end to the Wasga™ Compiler Design Suite for field programmable gate array (FPGA)-based prototyping.

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A few days ago, Menta of Montpellier, France, announced that it had selected IEEE-compliant Verilog, SystemVerilog, and VHDL parsers from Verific to serve as the front-end to Menta’s Origami Designer and Origami Programmer tools used to create embedded FPGAs for SoC designs.

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Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of a connectivity package that links Concept Engineering’s Nlview^TM schematic generator and visualization engine with Verific’s netlist database.

VVDI-Link gives Nlview, used within EDA tools to automatically create and visualize schematics for different levels of electronic circuits, direct access to the Verific database of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers. It is available from Concept Engineering as part of its Nlview family at no additional charge to existing customers.

“Concept Engineering and Verific have worked together since 2003 and continue to look for ways that will improve a designer’s productivity,” says Michiel Ligthart, Verific’s president and chief operating officer. “While a connectivity package may seem trivial, it’s actually a critical link.”

The same technology is deployed in Concept Engineering’s RTLvision® PRO tool, a powerful, easy-to-use register transfer level (RTL) viewer and debugger that combines Verilog, VHDL and SystemVerilog viewers in one integrated debugging cockpit.

“Software design teams rely on high-quality software components, such as automatic schematic generators and language parsers, which is why it was important to link our tools together,” comments Gerhard Angst, Concept Engineering’s chief executive officer and president. “Our new VVDI-Link package makes it easy to create innovative debugging cockpits for EDA tools.”

Concept Engineering’s Nlview provides automatic generation of schematic diagrams for different levels of electronic circuits, including transistor, gate, RTL, block and system. A fine granularity of user preferences can be mixed with machine computed “beauty” for the best human-readable diagrams. Interactive circuit exploration is supported by incremental schematic generation and navigation technology. Nlview provides a set of application programming interfaces (APIs) and interfaces for different GUI platforms.

Verific’s software is the front end to a variety of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers, today announced enhancements to its parser forthe IEEE 1801-2013standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).

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