Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, closed 2013 with a double-digit increase in revenue and56 active user companies, many of whom are longstanding customers.
Tabula upgrades to SystemVerilog
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added Verific’s SystemVerilog parser as front-end support to version 2.7.1 of its Stylus® compiler.
Verific increases revenue by 20%
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.
Aldec partners with Verific for HES platform
Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc.,a global leader in electronic design verification, to be included into its Hardware Emulation Solution (HES™).
Excellicon’s ConMan uses Verific
Excellicon, a first-time exhibitor of end-to-end Timing Constraints Solution at the Design Automation Conference (DAC), today announced it adopted Verific Design Automation’s industry-standard, IEEE-compliant front-end platform for use with its software for timing constraints authoring, verification and management.
Blue Pearl selects Verific
Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite.
Verific adds UPF 2.0 to Parser Platform
Verific Design Automation today announced immediate availability of a parser for the IEEE 1801-2009 Standard for Design and Verification of Low-Power Integrated Circuits. Also known as Unified Power Format 2.0 (UPF 2.0), it was developed by standards organization Accellera and carries the support of multiple EDA vendors.
Do-It-Yourself EDA Flows Take Off in 2012
When Verific started providing (System)Verilog and VHDL parsers in 2001, EDA companies were quick to jump on the bandwagon. Semiconductor companies with internal CAD teams and FPGA companies supporting customer design tools followed suit when they realized that they would be better off re-using Verific’s parsers than build their own.
vSync Circuits licenses Verific’s Parser Platform
Verific Design Automation, supplier of industry-standard, IEEE-compliant hardware description language (HDL) front-end solutions, today announced vSync Circuits Ltd. in Israel has licensed its parser platform for use with the vSync clock domain crossing (CDC) verification software.
Verific unveils Perl interface for its SystemVerilog and VHDL front-end solutions
The folks at Verific Design Automation, long known for their SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, have just unveiled a Perl interface to their industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.
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