Does Verific support cross

Q: Does Verific support cross module references (XMR)?

Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?title=Hierarchy_Tree

Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration.

The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar".

If the order of elaboration guarantees resolution of signals (e.g. module "foo" is elaborated before the module using "foo.bar" is), these runtime flags need to be enabled (set to 1) before design analysis:

   veri_preserve_user_nets
   db_preserve_user_nets
   db_allow_external_nets