How to ignore certain modules while analyzing input RTL files

The code example below shows how to ignore certain modules in the input RTL files. The ignored modules will not be present in the parsetree.

C++ code:

#include "Array.h"
#include "Message.h"
#include "veri_file.h"
#include "veri_nl_file.h"
#include "VeriWrite.h"
#include "DataBase.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
    Message::Msg(VERIFIC_INFO, 0, 0, "*** Read structural netlist 'bot.v' first");
    veri_nl_file::Read("bot.v");

    // Collect the names of the non-blackbox modules already in the Netlist Database
    // and add them to the 'ignore' list
    Library *lib = Libset::Global()->GetLibrary("work");
    if (lib) {
        Cell *cell;
        MapIter mi;
        FOREACH_CELL_OF_LIBRARY(lib, mi, cell) {
            if (cell->GetFirstNetlist()->IsBlackBox()) continue;
            const char *module_name = cell->Name();
            veri_file::AddToIgnoredParsedModuleNames(module_name);
        }
    }

    Message::Msg(VERIFIC_INFO, 0, 0, "*** Analyze 'bot.v' and 'top.v'");
    Array files(1) ;
    files.Insert("top.v") ;
    files.Insert("bot.v") ;
    if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;
    Message::Msg(VERIFIC_INFO, 0, 0, "*** Elaborate");
    if (!veri_file::ElaborateAll()) return 2;

    Netlist *top = Netlist::PresentDesign() ;
    if (!top) {
        Message::PrintLine("Cannot find any handle to the top-level netlist") ;
        return 5 ;
    }

    VeriWrite veriWriter;
    veriWriter.WriteFile("netlist_3.v", top) ;

    return 0 ;
}
 

RTL files:

// filename: top.v

module top (input a, b, output c, input i , output o);
  wire t1, t2;
  bot ua (.o(t1), .i(a));
  bot ub (.o(t2), .i(b));
  assign c = t1 & t2;
  foo uf (o, i);
endmodule

// this module 'foo' will be ignored
module foo (output o, input i);
  not (o, i);
endmodule


// filename: bot.v

module foo (output o, input i);
  buf (o, i);
endmodule

module bot (output o, input i);
  foo f (.o(o), .i(i));
endmodule
 

Run:

$ test3-linux
INFO: *** Read structural netlist 'bot.v' first
-- Reading structural Verilog file 'bot.v' (VNLR-1084)
bot.v(3): INFO: compiling module 'foo' (VNLR-1012)
bot.v(7): INFO: compiling module 'bot' (VNLR-1012)
bot.v(7): INFO: setting 'bot' as the top level module (VNLR-1015)
INFO: Ignoring module foo
INFO: Ignoring module bot
INFO: *** Analyze 'bot.v' and 'top.v'
-- Analyzing Verilog file 'top.v' (VERI-1482)
-- Analyzing Verilog file 'bot.v' (VERI-1482)
INFO: *** Elaborate
top.v(3): INFO: compiling module 'top' (VERI-1018)
-- Writing netlist 'top' to Verilog file 'netlist_3.v' (VDB-1030)
$
 

Output netlist:

//
// Verific Verilog Description of module top
//

module top (a, b, c, i, o);   // top.v(3)
    input a;   // top.v(3)
    input b;   // top.v(3)
    output c;   // top.v(3)
    input i;   // top.v(3)
    output o;   // top.v(3)

    wire t1;   // top.v(4)
    wire t2;   // top.v(4)

    bot ua (.o(t1), .i(a));   // top.v(5)
    bot ub (.o(t2), .i(b));   // top.v(6)
    and (c, t1, t2) ;   // top.v(7)
    foo uf (.o(o), .i(i));   // top.v(8)

endmodule

//
// Verific Verilog Description of module bot
//

module bot (o, i);   // bot.v(7)
    output o;   // bot.v(7)
    input i;   // bot.v(7)


    foo f (.o(o), .i(i));   // bot.v(8)

endmodule

//
// Verific Verilog Description of module foo
//

module foo (o, i);   // bot.v(3)
    output o;   // bot.v(3)
    input i;   // bot.v(3)


    buf (o, i) ;   // bot.v(4)

endmodule