Pretty-print a module and the packages imported by the module

C++:

#include <iostream>
#include <fstream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriScope.h"

#include "Map.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
    const char *file = (argc > 1) ? argv[1] : "test.sv" ;

    // Analyze the files (AnalyzeMultipleFiles API is the recommended one):
    Array files(1) ;
    files.InsertLast(file) ;
    if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

    MapIter mi ;
    VeriModule *module ;
    FOREACH_VERILOG_MODULE(mi, module){
        if (!module) continue ;
        if (module->IsPackage()) continue ; // no need to dive into package

        // Get the scope of the module:
        VeriScope *scope = module->GetScope() ;

        char *outputfilename = Strings::save(module->Name(), "_pp_out.v");
        std::ofstream f(outputfilename, std::ios::out) ;

        // Get the scope that this module/scope is using:
        // This also includes the compilation unit in the list, if any/required:
        Set *using_scopes = (scope) ? scope->GetUsing() : 0 ;

        // Print all those scopes/modules before printing the module itself:
        SetIter si ;
        VeriScope *using_scope ;
        FOREACH_SET_ITEM(using_scopes, si, &using_scope) {
            VeriIdDef *mod_id = using_scope->GetContainingModule() ;
            VeriModule *mod = (mod_id) ? mod_id->GetModule() : 0 ;
            if (!mod) continue ;
            if (mod->IsPackage()) {
                std::cout << ">>> Module '" << module->Name() << "' uses package '" << mod->Name() << "' <<<\n";
            }
            f << "// Printing package " << mod->Name() << endl ;
            mod->PrettyPrint(f, 0) ;
        }

        // Now  print the module:
        f << "// Printing module " << module->Name() << endl ;
        module->PrettyPrint(f, 0) ;
        f.close() ;
    }

    return 0 ;
}
 

Input Verilog:

package PKG1 ;
    typedef int my_int ;
endpackage

typedef byte my_byte ;

module test ;
    import PKG1::* ;
    my_int int1 ;
    my_byte byte1 ;
endmodule
 

Console output:

-- Analyzing Verilog file 'top.v' (VERI-1482)
>>> Module 'top' uses package 'PKG1' <<<
>>> Module 'top' uses package '$unit_top_v' <<<
 

Pretty-printed output:

// Printing package PKG1

package PKG1 ;
    typedef int my_int ;
endpackage


// Printing package $unit_test_sv

typedef byte my_byte ;


// Printing module test

module test ;
    import PKG1:: * ;
    my_int int1 ;
    my_byte byte1 ;
endmodule