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1. A customer wants to analyze/elaborate
2. Access attributes in parsetree
3. Access attributes of ports in parsetree
4. Accessing and evaluating module's parameters
5. Bit-blasting a multi-port RAM instance
6. Buffering signals and ungrouping
7. Comment out a line using test-based design modification and parsetree modification
8. Comment out a line using text based design modification and parsetree modification
9. Compile-time/run-time flags
10. Constant expression replacement
11. Create DOT diagram of parse tree
12. Create a Netlist Database from scratch (not from RTL elaboration)
13. Cross-reference between the original RTL files and the elaborated netlist
14. Defined macros become undefined - MFCU vs SFCU
15. Design with System Verilog and Verilog 2001 files
16. Design with VHDL-1993 and VHDL-2008 files
17. Difference between RTL and gate-level simulations - Flipflop with async set and async reset
18. Does Verific build CDFG?
19. Does Verific support XMR?
20. Does Verific support cross
21. Does Verific support cross module references (XMR)?
22. Escaped identifiers in RTL files and in Verific data structures
23. Evaluate 'for-generate' loop
24. Extract clock enable
25. Fanout cone and grouping
26. Finding hierarchical paths of a Netlist
27. General
28. Getting instances' parameters
29. Hierarchy tree RTL elaboration
30. How do I know
31. How do I know what language a Netlist in the netlist database comes from?
32. How to change name of id in Verilog parsetree
33. How to check for errors in analysis/elaboration
34. How to create a Netlist database from scratch (not from RTL input)
35. How to create new module in Verilog parsetree
36. How to detect multiple-clock-edge condition in Verilog parsetree
37. How to enable long paths on Windows?
38. How to find port dimensions
39. How to get all Verilog files being analyzed
40. How to get best support from Verific
41. How to get driving net of an instance
42. How to get enums from Verilog parsetree
43. How to get full hierarchy ID path
44. How to get library containing nested module
45. How to get linefile data of macros - Macro callback function
46. How to get linefile information of macro definitions
47. How to get module ports from Verilog parsetree
48. How to get packed dimensions of enum
49. How to get type/initial value of parameters
50. How to identify packages being imported into a module

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