User contributions
- 16:37, 8 July 2016 (diff | hist) . . (+852) . . N Does Verific support cross (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...") (current)
- 16:37, 8 July 2016 (diff | hist) . . (+1,593) . . N What are the data (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 16:36, 8 July 2016 (diff | hist) . . (+240) . . N How do I know (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...") (current)
- 16:34, 8 July 2016 (diff | hist) . . (+64) . . Main Page
- 16:30, 8 July 2016 (diff | hist) . . (-39) . . Main Page
- 16:25, 8 July 2016 (diff | hist) . . (+35) . . Main Page
- 16:16, 8 July 2016 (diff | hist) . . (+742) . . N A customer wants to analyze/elaborate (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...") (current)
- 16:15, 8 July 2016 (diff | hist) . . (+878) . . N I have a design consisting of (Created page with "'''Q: I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?''' The set of SystemVerilog const...") (current)
- 16:15, 8 July 2016 (diff | hist) . . (+1,602) . . N Why are the ports (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...") (current)
- 16:10, 8 July 2016 (diff | hist) . . (+672) . . N While looking at a Netlist (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...") (current)
- 16:09, 8 July 2016 (diff | hist) . . (+847) . . N I'm using -v, -y, (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...") (current)
- 16:08, 8 July 2016 (diff | hist) . . (-82) . . Main Page
- 15:35, 8 July 2016 (diff | hist) . . (+852) . . N Does Verific support cross module references (XMR)? (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...") (current)
- 15:34, 8 July 2016 (diff | hist) . . (+1,593) . . N What are the data structures in Verific? (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 15:33, 8 July 2016 (diff | hist) . . (+240) . . N How do I know what language a Netlist in the netlist database comes from? (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...") (current)
- 15:32, 8 July 2016 (diff | hist) . . (-80) . . Main Page
