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'''General'''
 
'''General'''
* [[How do I know | How do I know what language a Netlist in the netlist database comes from?]]
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* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
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* [[Source code customization & Stable release services | Source code customization & Stable release services]]
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* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
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* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
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* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support cross| Does Verific support cross module references (XMR)?]]
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* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
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* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
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* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
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* [[Release version | How do I tell the version of a Verific software release? ]]
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* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
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* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
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* [[LineFile data from input files | LineFile data from input files]]
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* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
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* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
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* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
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* [[Yosys-Verific Integration | Yosys-Verific integration]]
  
 
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'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
'''VHDL, Verilog, Liberty, EDIF'''
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* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[I'm using -v, -y, | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
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* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[While looking at a Netlist | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]]
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* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Why are the ports | Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
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* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
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* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]]
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* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
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* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
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* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
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* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
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* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
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* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
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* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
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* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
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* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
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* [[Notes on analysis | SystemVerilog: Notes on analysis]]
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* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
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* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
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* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
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* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
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* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
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* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
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* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
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* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
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* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
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* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
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* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
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* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
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* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
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* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
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* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
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'''Netlist Database'''
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* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
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* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
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* [[System attributes | Netlist Database: System attributes]]
  
 
'''Output'''
 
'''Output'''
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* [[Output file formats | What language formats does Verific support as output?]]
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'''Scripting languages: TCL, Perl, Python'''
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* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]
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'''Code examples'''
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* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
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* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
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* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
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* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
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* [[Extract clock enable | Database/C++: Extract clock enable]]
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* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
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* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
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* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
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* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
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* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
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* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
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* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
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* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
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* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
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* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
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* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
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* [[Type Range example | Database/Verilog/C++: Type Range example  (simple)]]
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* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
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* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
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* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
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* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
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* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
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* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
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* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
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* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
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* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
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* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
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* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
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* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
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* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
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* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
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* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
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* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
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* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
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* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
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* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
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* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
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* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
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* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
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* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
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* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
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* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
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* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
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* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
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* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
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* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
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* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
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* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
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* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
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* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
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* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
  
'''TCL, Perl, Python, Java'''
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'''INVIO Code examples'''
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* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Latest revision as of 17:08, 18 October 2024

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples

INVIO Code examples