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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
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* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
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* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
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'''INVIO Code examples'''
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* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Latest revision as of 18:08, 18 October 2024

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples

INVIO Code examples