Difference between revisions of "Main Page"

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* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
 
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
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* [[Modules with "_1", "_2", ..., suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
  

Revision as of 12:47, 27 September 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples