Difference between revisions of "Main Page"

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* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
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'''INVIO Code examples'''
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* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Revision as of 15:54, 11 October 2024

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples

INVIO Code examples