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- A customer wants to analyze/elaborate
- Access attributes in parsetree
- Access attributes of ports in parsetree
- Accessing and evaluating module's parameters
- Bit-blasting a multi-port RAM instance
- Black box, empty box, and unknown box
- Buffering signals and ungrouping
- Comment out a line using test-based design modification and parsetree modification
- Comment out a line using text based design modification and parsetree modification
- Compile-time/run-time flags
- Constant expression replacement
- Create DOT diagram of parse tree
- Create a Netlist Database from scratch (not from RTL elaboration)
- Cross-reference between the original RTL files and the elaborated netlist
- Defined macros become undefined - MFCU vs SFCU
- Design with System Verilog and Verilog 2001 files
- Design with VHDL-1993 and VHDL-2008 files
- Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- Does Verific build CDFG?
- Does Verific support XMR?
- Does Verific support cross
- Does Verific support cross module references (XMR)?
- Escaped identifiers in RTL files and in Verific data structures
- Evaluate 'for-generate' loop
- Extract clock enable
- Fanout cone and grouping
- Finding hierarchical paths of a Netlist
- General
- Getting instances' parameters
- Hierarchy tree RTL elaboration
- How Verific elaborator handles blackboxes/unknown boxes
- How do I know
- How do I know what language a Netlist in the netlist database comes from?
- How to change name of id in Verilog parsetree
- How to check for errors in analysis/elaboration
- How to create a Netlist database from scratch (not from RTL input)
- How to create new module in Verilog parsetree
- How to detect multiple-clock-edge condition in Verilog parsetree
- How to enable long paths on Windows?
- How to find port dimensions
- How to get all Verilog files being analyzed
- How to get best support from Verific
- How to get driving net of an instance
- How to get enums from Verilog parsetree
- How to get full hierarchy ID path
- How to get library containing nested module
- How to get linefile data of macros - Macro callback function
- How to get linefile information of macro definitions
- How to get module ports from Verilog parsetree
- How to get packed dimensions of enum
- How to get type/initial value of parameters
- How to identify packages being imported into a module
- How to ignore a (not used) parameter/generic in elaboration.
- How to ignore certain modules while analyzing input RTL files
- How to ignore parameters/generics in elaboration
- How to insert/add a statement, or a module item, into a sequential block and a generate block
- How to make lives easier
- How to parse a string
- How to replace a statement that has a label
- How to save computer resources
- How to tell if a module has encrypted contents
- How to traverse scope hierarchy
- How to use MessageCallBackHandler Class
- How to use RegisterCallBackMsg()
- How to use RegisterPragmaRefCallBack()
- I'm using -v, -y,
- I have a design consisting of
- In Verilog parsetree adding names to unnamed instances
- Included files associated with a Verilog source file
- Instance - Module binding order
- LineFile data from input files
- Logic optimization across hierarchy boundaries
- Macro Callback example
- Main Page
- Memory elements of a RamNet
- Message handling
- Modules/design units with " default" suffix in their names
- Modules with " 1", " 2", ..., suffix in their names
- Modules with ' 1' ' 2' suffix in their names
- Notes on analysis
- Original RTL language
- Output file formats
- Parse select modules only and ignore the rest
- Parsing from data in memory
- Post processing port resolution of black boxes
- Preserving nets
- Preserving user nets --preventing nets from being optimized away
- Preserving user nets - preventing nets from being optimized away
- Pretty-print a module and the packages imported by the module
- Prettyprint all modules in the design hierarchy
- Prettyprint to a string
- Process -f file and explore the Netlist Database
- Process -f file and explore the Netlist Database (C++)
- Process -f file and explore the Netlist Database (py)
- Python pretty-printer for gdb
- Release version
- Remove Verific data structures
- Replacing Verific built-in primitives/operators with user implementations
- Retrieve package name for user-defined variable types
- Simple example of visitor pattern
- Simple examples of VHDL visitor pattern
- Simple port modification
- Simulation models for Verific primitives
- Source code customization & Stable release services
- Static elaboration
- Statically elaborate with different values of parameters
- Support IEEE 1735 encryption standard
- SystemVerilog "std" package
- System attributes
- Tcl library path
- Test-based design modification
- Top level module with interface ports
- Traverse instances in parsetree
- Type Range example
- Type Range example with multi-dimensional arrays
- Using TypeRange table to retrieve the originating type-range for an id
- Using stream input to ignore input file
- VHDL, Verilog, Liberty, EDIF
- Verific data structure
- Verific data structures
- Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path
- Verilog/C++: How to use IsUserDeclared() : Example for port associations
- Verilog/C++: How to use IsUserDeclared() and port associations
- Verilog Port Expressions
- Verilog ports being renamed
- Visiting Hierarchical References (VeriSelectedName)
- What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- What are the data
- What are the data structures in Verific?
- What languages can I use with Verific software?
- Where in RTL does it get assigned?
- Where in RTL is it get assigned?
- While looking at a Netlist
- Why are the ports
- Write out an encrypted netlist
- Yosys-Verific Integration
